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Radiation-Hardened ASICs

Radiation-Hardened ASICS

Radiation-Hardened ASICS

BAE Systems' advanced technologies enable the manufacture of true system-on-a-chip products. We are proud to offer you a complete, state-of-the-art solution for your future space processing needs.

BAE Systems offers foundry services with application-specific integrated circuit (ASIC) products that employ different technologies characteristics to address varied customer needs. All of the products are compatible with a wide variety of commercially available design tools, and feature circuit libraries with <1E-10 upsets / bit-day SEU immunity. In addition, an expanding set of synthesizable, reusable cores are available to increase design productivity and lower risk. BAE Systems also offers ASIC design services for those customers who prefer or need to outsource ASIC development.

The 0.25 µm R25 ASIC products provide high-performance, high-capacity ASIC solutions to the space market. This is a standard cell offering that delivers excellent performance, power, and density to users whose total-dose radiation requirements fall into the 200-krad (Si) range, using R25 CMOS technology.

The 0.25µm RH25 structured ASIC is a family of 3.3V structured ASICS that can be customized with only three unique mask levels, greatly reducing mask cost and fabrication time. This offering addresses requirements up to 1 Mrad (Si), using the Manassas Semiconductor Center RH25 technology.

The 0.15µm RH15 ASIC and structured ASIC provide start-of-the-art density, power, and performance to the user community. The RH15 ASIC offering is a full standard cell library capable of handling ASICs up to 15 million gates. The RH15 structured ASIC provides a three-mask programmable offering that greatly reduces mask cost and fabrication time while still meeting the needs for low power and high performance.

We offer a full range of design and test services, with multiple entry points into the process. Our packaging technologies include wirebond, C4/flipchip, ceramic leadless chip carrier, ceramic quad flat pack, ceramic column grid array, and plastic ball grid array.

Technology Summary

R25 (Standard cell)

  • 2.5 V core, 3.3 V I/O
  • 0.25 mm devices
  • 4–6 level metal
  • Bulk complementary metal oxide semiconductor (CMOS)
  • 200 krad TID
  • 6 M gates maximum

RH25 (Structured)

  • 3.3 V core, 3.3 V I/O
  • 0.25 mm devices
  • 4–6 level metal
  • Bulk CMOS
  • 1 mrad TID
  • 1 M gates maximum
  • Family of masterslices

RH15 (Standard cell)

  • 1.5 V core, 3.3 V I/O
  • 0.15 mm devices
  • 4–6 level metal
  • Bulk CMOS
  • 1 mrad TID
  • 4 M gates maximum
  • Mixed signal offering

RH15 (Structured)

  • 1.5 V core, 3.3 V I/O
  • 0.15 mm devices
  • 4–6 level metal
  • Bulk CMOS
  • 1 mrad TID
  • 15 M gates maximum
  • Family of masterslices

For further information please contact:

Tim Scott
9300 Wellington Rd
Manassas, VA 20110
Tel: +1 703-367-4615
timothy.scott@baesystems.com

 

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